Combinatorial optimization using CMOS Ising solver

• Hüsrev Cılasun, Ziqing Zeng, Ramprasath S et al., "3SAT on an all‑to‑all‑connected CMOS Ising solver chip," Scientific Reports, April 2024. 10.1038/s41598-024-60316-y

Analog/Mixed-Signal Layout Automation

During my postdoc, I was primarily involved in the research and development of tools and algorithms for AMS layout automation. Using the developed tool, we were able to lay out a MIMO whose performance was comparable to one generated by an expert designer.

Below are few publications from my work in this problem:

• K. Kunal et al., "Reinforcing the Connection between Analog Design and EDA (Invited Paper)," Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2024. 10.1109/ASP-DAC58780.2024.10473957
• J. Poojary, S. Ramprasath, S. S. Sapatnekar, and R. Harjani, "Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN," Proceedings of Radio Frequency Integrated Circuits Symposium (RFIC), 2023. 10.1109/RFIC54547.2023.10186141
• S. Ramprasath, M. Madhusudan, A. K. Sharma, J. Poojary, S. Yaldiz, R. Harjani, S. M. Burns, and S. S. Sapatnekar, "A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/Mixed-Signal Layouts," ACM Transactions on Design Automation of Electronic Systems, March 2023. 10.1145/3580477
• S. Ramprasath, A. K. Sharma, M. Madhusudan, S. Yaldiz, J. Poojary, R. Harjani, S. M. Burns, and S. S. Sapatnekar, "Analog/Mixed-Signal Layout Optimization using Optimal Well Taps," Proceedings of the ACM International Symposium on Physical Design, 2022 (Nominated for Best Paper Award). 10.1145/3505170.3506728.
• T. Dhar, S. Ramprasath, J. Poojary, S. Yaldiz, S. Burns, R. Harjani, and S. S. Sapatnekar, "A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement," Proceedings of Design, Automation and Test in Europe, 2022. 10.23919/DATE54114.2022.9774621

Synthesis of ML inference hardware

• K. Kunal, J. Poojary, S. Ramprasath, R. Harjani and S. S. Sapatnekar, "Automated synthesis of mixed-signal ML inference hardware under accuracy constraints," Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2024. 10.1109/ASP-DAC58780.2024.10473942.

Statistical Static Timing Analysis

During my PhD, I worked on (a) efficient algorithms to find critical nodes in timing graphs under process variations with normal and skew-normal distributions, and (b) optimization of circuits for better timing yield. Select list of publications from my work:

• S. Ramprasath and V. Vasudevan, "Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient," ACM Transactions on Design Automation of Electronic Systems, May 2016. 10.1145/2896819
• S. Ramprasath, M. Vijaykumar, and V. Vasudevan, "A Skew-Normal Canonical Model for Statistical Static Timing Analysis," IEEE Transactions on Very Large Scale Integration (VLSI), December 2015. 10.1109/TVLSI.2015.2501370
• S. Ramprasath and V. Vasudevan, "An efficient algorithm for statistical timing yield optimization", Proceedings of the Design Automation Conference, 2015. 10.1145/2744769.2744796
• S. Ramprasath and V. Vasudevan, "Statistical Criticality Computation Using the Circuit Delay," IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, May 2014. 10.1109/TCAD.2013.2296436
• S. Ramprasath and V. Vasudevan, "On the computation of criticality in statistical timing analysis", Proceeedings of the International Conference on Computer-Aided Design, 2012. 10.1145/2429384.2429418

Graph Neural Network Inference Accelerator

• S. Mondal, S. D. Manasi, K. Kunal, S. Ramprasath, Z. Zeng, and S. S. Sapatnekar, “GNNIE: GNN Inference Engine with Load-balancing and Graph-specific Caching,” Proceedings of the Design Automation Conference, 2022. 10.1145/3489517.3530503
• S. Mondal, S. D. Manasi, K. Kunal, S. Ramprasath, and S. S. Sapatnekar, "A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, with Efficient Load Balancing and Graph-Specific Caching," IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, December 2022. 10.1109/TCAD.2022.3232467
• S. Mondal, S. Ramprasath, Z. Zeng, K. Kunal, and S. S. Sapatnekar, "A Multicore GNN Training Accelerator," Proceedings of the International Symposium on Low Power Electronics and Design, 2023.