This is an elective offered by me at the Department of Electrical Engineering, IIT Madras.
The textbook followed is: VLSI Physical Design: From Graph Partitioning to Timing Closure, A. B. Kahng, J. Lienig, I. L. Markov, and J. Hu.
Python notebooks used for tutorials in the class are available at: EE5333_tutorials
A version of recorded lectures of this course are available at this URL. Topics covered in the recordings:
| Topic | Lecture No. |
|---|---|
| Intro. and Foundation | 01 - 04 |
| Graph and Hypergraph partitioning | 05 - 08 |
| Floorplanning | 09 - 13 |
| Placement | 14 - 20 |
| Routing | 21 - 25 |
| Mid-sem | 26 |
| Analog and Mixed-signal Layout | 27 - 28 |
| Power grid | 29 |
| Gate sizing | 30 |